1. Field of the Invention
The present invention relates, most generally, to semiconductor device manufacturing, and more particularly to via/contact and/or damascene structures and manufacturing methods for forming the same.
2. Description of the Related Art
With advances associated with electronic products, semiconductor technology has been widely applied in manufacturing memories, central processing units (CPUs), liquid crystal displays (LCDs), light emission diodes (LEDs), laser diodes and other devices or chipsets. In order to achieve high-integration and high-speed goals and keep up with the advances in electronic products, dimensions of semiconductor integrated circuits continue to shrink. In addition, low-k dielectric materials and low-resistance metallic materials are used for reducing parasitic capacitances and resistance-capacitance (RC) time delays in order to enhance speeds of integrated circuits.
FIG. 1 is a cross-sectional view of a prior art semiconductor structure for forming a via structure.
Referring to FIG. 1, metal lines 110 are formed over a substrate 100. A dielectric layer 120 is formed on the substrate 100 and the metal lines 110. Holes (not labeled) are formed within the dielectric layer 120 and are via holes but may alternatively represent contact holes or trenches within which damascene leads are to be formed. A conductive diffusion barrier layer 130, e.g., a tantalum/tantalum nitride (Ta/TaN) diffusion barrier layer, is formed on the dielectric layer 120 and within the via holes. A copper seed layer 140 is formed on the Ta/TaN diffusion barrier layer 130. A copper layer 150 is formed on the copper seed layer 140 and fills in the via holes.
In order to isolate via structures formed in adjacent via holes, a chemical-mechanical polishing (CMP) process is used to remove the copper layer 150, the copper seed layer 140 and the Ta/TaN diffusion barrier layer 130 formed over the surface 121 of the dielectric layer 120. Since the material property of copper is different from that of Ta/TaN or other materials which may be used as the barrier layer 130, different recipes, slurries, polishing forces, pads or other factors of CMP process must be selected for individually removing the copper layer 150, the copper seed layer 140 and the Ta/TaN diffusion barrier layer 130 formed over the surface 121 of the dielectric layer 120.
Based on the foregoing, improved methods and structures for forming contact/via and/or damascene structures are desired.